In recent years, flash memory devices, i.e., nonvolatile semiconductor memory devices in which a program operation and an erase operation are performed electrically, have begun to be used in battery-powered portable electronics. Since integrated circuit chips used in portable electronics are being designed to operate at lower voltage, it is desirable that flash memory devices incorporated in portable electronics consume less power. Also, it is required that the erase/program operation of the flash memory device be performed rapidly despite the low operating voltage.
As is well known, when the program/erase operation of a flash memory device is performed, a voltage (hereinafter, referred to as a high voltage Vpp) higher than the power supply voltage is used. The high voltage Vpp is not provided externally, but is instead generated in the flash memory device by use of a high voltage generator (for example, a charge pump circuit). In a charge pump circuit, the pumping efficiency--defined as a ratio of pumping current (pumped voltage) to consumed power current (voltage)--is about 10%. Thus, considerable power is consumed by the flash memory device's on-chip high voltage generator. Therefore, in order to realize a low-power flash memory device, a method capable of effectually controlling the high voltage Vpp, which is used at a program/erase operation of the flash memory device, is required.
Referring to FIG. 1, a block diagram of a conventional flash memory device is illustrated. In FIG. 1, the reference numbers 10, 12, 14, and 16 indicate a memory cell array, an address buffer circuit, a row decoder circuit, and a column decoder circuit, respectively. And, the reference numbers 18, 20, and 22 indicate a high voltage generator, a mode setting signal generator, and a word line voltage switching circuit, respectively. A circuit diagram showing a part of the memory cell array 10 and detailed circuits of the high voltage generator 18, the mode setting signal generator 20, and the word line voltage switching circuit 22, together with the row decoder circuit 14, is illustrated in FIG. 2.
In FIG. 2, reference number 11 indicates memory cells (for example, ETOX-type cells) arranged in matrix form, and reference number 12 indicates word lines to which gates of memory cells 11 in the same row of array 10 are connected in common. Reference number 13 indicates bit lines that are arranged perpendicular to word lines 12, and that are connected in common to drain regions of memory cells 11 in the same column of array 10. Reference number 15 indicates source lines (as well known, a ground voltage is provided into 14) that are connected in common to source regions of memory cells 11 in the same row of array 10.
In memory cell array 10, during a read mode of operation, a power supply voltage (for example, 5V) is applied to a word line 12, and an intermediate voltage (for example, 1V) is applied to a bit line 13. During a program mode of operation, the high voltage Vpp (for example, 10V) is applied to word line 12, and the power supply voltage is applied to bit line 13. During an erase mode of operation, a negative voltage (for example, -10V) is applied to all of the word lines 12, and the bit lines 13 and the source lines 15 are maintained in a floating state.
Continuing to refer to FIG. 2, the high voltage Vpp applied to the word line during the read and program modes of operation is generated in high voltage generator 18. High voltage generator 18 operates from the power supply voltage VCC, and produces the high voltage Vpp having a voltage level required at the respective modes of operation. The high voltage Vpp from generator 18 is applied via word line switching circuit 22 to a word line selected by row decoder circuit 14. Word line voltage switching circuit 22 transfers to the row decoder circuit 14 either power supply voltage VCC or high voltage Vpp (from high voltage generator 18) depending on the state of a mode setting signal MODE received from mode setting signal generator 20.
As illustrated in FIG. 2, mode setting signal generator 20 is composed of two NOR gates 50 and 51. NOR gate 50 has two input terminals for receiving signals PGM and PGMVFY, and NOR gate 51 outputs mode setting signal MODE by NORing the output of NOR gate 50 and a signal DIS. The signal PGM indicates a program mode of operation, the signal PGMVFY indicates a program verification mode of operation, and the signal DIS indicates a word line voltage discharge operation. Word line voltage switching circuit 22 is composed of two level shifters 52 and 53 and two PMOS transistors 54 and 55, connected as shown in FIG. 2.
FIG. 3 is a flowchart showing processor steps of a program operation associated with the NOR-type flash memory device illustrated in FIG. 2, and FIG. 4 is a diagram showing word line voltage changes during program mode operation. Programming operation of a conventional flash memory device will be more fully described below with reference to the accompanying drawings. For ease of description, a programming operation associated with only one memory cell 11 will be described.
When a program operation is initiated, a program verification operation is first performed in step S10 in order to discriminate whether a memory cell needs to be programmed. Herein, in the case where memory cell 11 is an on-cell, the threshold voltage of the memory cell is between 1V and 3V. If it is an off-cell, the threshold voltage thereof is between 6V and 7V. During the program verification operation, a program verification voltage of about 6V, for example, is applied to the word line 12 to which the gate of memory cell 11 is connected. At the same time, a sensing current is supplied onto the bit line 13 associated with memory cell 11.
In particular, in step S 10, the signals PGM, PGMVFY, and DIS are set at a logic low level, a logic high level, and a logic low level, respectively, as illustrated in FIG. 4. This forces mode setting signal generator 20 to generate a logic high level at mode setting signal MODE, so that PMOS transistor 54 of circuit 22 is turned off and NMOS transistor 55 thereof is turned on. Accordingly, the high voltage Vpp (that is, a program verification voltage of about 6V) generated in high voltage generator 18 is supplied to word line 12 via turned-on transistor 55 and row decoder circuit 14.
In a subsequent step S12, it is determined whether the memory cell 11 is an on-cell or an off-cell. If it is an off-cell, the program operation is ended. In the case where the memory cell is an off-cell, it has a threshold voltage of about 6 to 7V, and during a verify operation, the voltage level on the bit line becomes higher than a precharged voltage level.
If the memory cell 11 is an on-cell (i.e., it has a threshold voltage of about 1 to 3V and during a verify operation, voltage level on the bit line becomes lower than the precharged voltage level), the procedure continues at step S14. At step S14, a program operation is performed to set memory cell 11's threshold voltage to about 6 to 7V (corresponding to an off-cell). During the program operation, the high voltage Vpp (that is, a program voltage of about 10V) generated in high voltage generator 18 is supplied to the word line 12 associated with memory cell 11, and a voltage of about 5V is supplied to the bit line 13 associated with memory cell 11. Also, the source line 15 connected to the source of memory cell 11 is grounded.
In particular, since the signals PGM, PGMVFY, and DIS are set respectively at a logic high level, a logic low level, and a logic low level during the program operation, the mode setting signal MODE remains at a logic high level. This enables PMOS transistor 54 of circuit 22 to be turned off and NMOS transistor 55 thereof to be turned on. As a result, the program voltage of about 10V is supplied to word line 12 via turned-on transistor 55 and row decoder circuit 14. The above-described voltage condition is maintained for a predetermined time. As is well known in the art, during programming hot electrons having high energy are injected into a floating gate from a channel region adjacent to the drain of memory cell 11. Hot electron injection increases the threshold voltage of memory cell 11.
In a subsequent step S16, the program verification operation is performed again (herein, as shown in FIG. 4, the voltage supplied to the word line is lowered from 10V to 6V). At step S18, it is determined whether the program step was successful. If the memory cell 11 is an off-cell, the program operation is ended. Otherwise, the procedure steps to S19, where it is determined whether the program operation has been performed a predetermined maximum number of times. If not, a loop counter is incremented at step S20 and control is passed back to step S14. If the maximum loop count is exceeded, the program operation control is terminated.
The program operation is performed as described above when a word line discharge operation is performed prior to step S16. During the discharge operation, the word line is discharged from the program voltage of about 10V down to the power supply voltage VCC. During the discharge operation, the signals PGM, PGMVFY, and DIS applied to mode setting signal generator 20 are set at a logic high level, a logic low level, and a logic high level, respectively, as illustrated in FIG. 4. Mode setting signal generator 20 produces a logic low level at signal MODE in response to the signals PGM, PGMVFY, and DIS. This makes PMOS transistor 55 of circuit 22 turn off and PMOS transistor 54 thereof turn on. Therefore, the program voltage of about 10V on word line 12 is lowered to the power supply voltage VCC via turned-on transistor 54. After this, the program verification operation will be performed as described above.
If the program voltage of about 10V has not discharged to the program verification voltage of about 6V or the power supply voltage of about 5V before the intended time for the program verification operation, the program verification operation is delayed until the voltage on the word line is discharged to 6V. The word line also originates various leakage current. This slows the overall operation speed of the flash memory device. Therefore, before the program verification operation can be performed after a program operation, the voltage on the word line must be discharged to the same voltage as the program verification voltage or lower. This problem always exists when the voltage supplied on a word line at one operation mode is higher than the voltage to be supplied on the word line at the next operation mode.
Whenever a discharge operation is performed, the program verification voltage has to be generated from high voltage generator 18 because the voltage on the word line drops below the program verification voltage when the discharge operation is performed. This consumes power in the flash memory device, particularly with a low pumping efficiency high voltage generator 18. In FIG. 4, the hatched portion indicates the amount of charge consumed by the discharge operation. Therefore, as the number of repeated program operations increases, the power consumed by the conventional flash memory device may increase considerably.